Delay hidden techniques based on configuration contexts reuse and differential reconfiguration in coarse-grained reconfigurable processor

Reconfiguration delay seriously downgrades coarse grained reconfigurable processor´s performance because large numbers of cycles are needed to transmit the configuration contexts. Therefore, two delay hidden techniques, configuration contexts reuse and differential reconfiguration, are introduced into our REmus coarse-grained reconfigurable processor by employing the repeatability and similarity between the subsequent configuration contexts. An on-chip Scratchpad Configuration Memory (SCM) less than 4KB is embedded to buffer the repeated obsolete configuration contexts, which can be retransmitted to the reconfigurable elements much faster than reread the configuration words from the outer main memory. Furthermore, a partial reconfiguration mechanism is also designed to mitigate the transmission overheads of two adjacent or non-adjacent similar configuration contexts by only transmitting the distinct parts of the succeeding context (differential reconfiguration). At the same time, corresponding compiling scheme for fully utilizing the two features is also being designed and integrated into the original task compiler. Some preliminary experiments on REmus processor indicate that at most 35% speed-up is achieved than the original design without the two enhancing fabrics.