A two-phase floorplanning approach for Application-specific Network-on-Chip

In this paper, we present a two-phase floorplanning approach based on genetic algorithm to arrange each IP core reasonably into a fixed-outline rectangle for Application-specific Network-on-Chip (NoC) design. Our algorithm consists of core clustering and cluster floorplanning. These steps are done to arrange IP cores with optimizing communication power consumption and chip area. Experimental results on several multimedia benchmarks show that our proposed algorithm saves about 30% of power consumption and 5% of chip area compared to random floorplanning on average.