Session 17 overview: Embedded memory and DRAM I/O: Memory subcommittee

Demand for smaller and lighter personal devices with increasing functionality in the cloud drives advancements in both embedded memory technology and high-speed DRAM interfaces. Lower power through voltage reduction and increased performance through higher memory density and bandwidth are key enablers. This year´s conference highlights 14nm FinFET technologies with the smallest bit cells achieved to date for both SRAM — at 0.05μm² — and embedded DRAM — at 0.01747μm². A new assist technique to drive VMIN reduction and novel bit cells for both 2-port SRAM and TCAM applications are also presented. In addition, two area-efficient techniques to boost DRAM bandwidth are reported.