A 12-bit 200-MS/s sample-and-hold amplifier with a hybrid Miller-Feedforward compensation technique

Author

Yongzhen Chen ; Chixiao Chen ; Qiang Zhang ; Ye Fan ; Junyan Ren

Author_Institution

State-Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

fYear

2013

fDate

28-31 Oct. 2013

Firstpage

1

Lastpage

4

Abstract

A CMOS fully differential high gain-bandwidth (GBW) operational amplifier applied in a sample-and-hold (S&H) circuit is presented in the paper. High bandwidth and phase margin of the amplifier are obtained by combining two compensation techniques: Miller compensation and Feedforward compensation. In addition, in order to achieve a high gain, the gain-boosting technique is employed. The circuit is designed in SMIC 65 nm process consuming 47.25 mW at a 1.2 V power supply and is suitable for 12-bit 200-MS/s pipelined ADC applications. At 200 MS/s, the S&H circuit achieves 77.68 dB SNDR for an input of 92.38 MHz.

Keywords

CMOS integrated circuits; compensation; differential amplifiers; feedforward amplifiers; monolithic integrated circuits; operational amplifiers; sample and hold circuits; CMOS fully differential high gain-bandwidth operational amplifier; GBW operational amplifier; Miller compensation; S&H circuit; SMIC 65 nm process; compensation techniques; feedforward compensation; frequency 92.38 MHz; gain-boosting technique; pipelined ADC applications; power 47.25 mW; sample-and-hold circuit; size 65 nm; voltage 1.2 V; word length 12 bit; CMOS integrated circuits; Capacitors; Clocks; Feedforward neural networks; Poles and zeros; Time-frequency analysis; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC (ASICON), 2013 IEEE 10th International Conference on

Conference_Location

Shenzhen

ISSN

2162-7541

Print_ISBN

978-1-4673-6415-7

Type

conf

DOI

10.1109/ASICON.2013.6811866

Filename

6811866