A 10-bit pipelined ADC with improved S/H circuit for CMOS image sensor

Author

Yiling Ding ; Qi Zhang ; Ning Wang ; Dunshan Yuan ; Guohong Li ; Hui Wang ; Songlin Feng

Author_Institution

Shanghai Adv. Res. Inst., Shanghai, China

fYear

2013

fDate

28-31 Oct. 2013

Firstpage

1

Lastpage

4

Abstract

A 10-bit pipelined ADC with an improved S/H circuit for CMOS image sensor is presented in this paper. The improved S/H circuit is proposed to adjust the range of the input signal, eliminate dark current noise and calibrate offset voltage. The dark current noise and offset voltage can be calibrated with a DAC feedback loop and two feedback capacitances. During the sample phase, a special modulation voltage is generated to widen the range of input signal. The simulation results show that the maximum error voltage to be calibrated is up to 0.5V. The ADC achieves a SNDR of 58.4dB and ENOB of 9.4bits at 30MHz sample rate. The DNL and INL are 0.27LSB and 0.48LSB respectively.

Keywords

CMOS image sensors; analogue-digital conversion; detector circuits; pipeline processing; CMOS image sensor; S/H circuit; analog-digital converter; dark current noise elimination; modulation voltage; pipelined ADC; CMOS image sensors; Calibration; Dark current; Electronics packaging; Lighting; Noise;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC (ASICON), 2013 IEEE 10th International Conference on

Conference_Location

Shenzhen

ISSN

2162-7541

Print_ISBN

978-1-4673-6415-7

Type

conf

DOI

10.1109/ASICON.2013.6811872

Filename

6811872