An improved implementation method of the gold sequence generator

Conventional GSG (gold sequence generator) creates only 1 bit data per clock cycle. Therefore it may cause delay to the data communications. In this paper, we propose an efficient implementation method of the GSG for high speed data communications. Through simple matrix multiplications, we could not only derive a well-organized recursive formula but also implement the GSG with parallel outputs. Experimental results show that though the total area and clock period of the proposed scheme are 3~13% and 21~23% larger than those of the existing scheme respectively, our GSG improves 2, 4 and 6 times the throughput compared with the existing GSG when the modulation orders are QPSK, 16-QAM and 64-QAM respectively.