A 10Gb/s analog equalizer in 0.18um CMOS

Author

Linghan Wu ; Ziqiang Wang ; Ke Huang ; Shuai Yuan ; Xuqiang Zheng ; Chun Zhang ; Zhihua Wang

Author_Institution

Tsinghua Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China

fYear

2013

fDate

28-31 Oct. 2013

Firstpage

1

Lastpage

4

Abstract

This paper describes a 10Gb/s analog equalizer applied to transmitter. The equalizer consists of a continuous time linear equalizer (CTLE), with a shunt and double-series peaking network, which is used to enhance the bandwidth of the circuit and to boost the high frequency content of the signal. This paper deduces the circuit´s transfer function and proposes a design guidance to circuit design. The circuit is fabricated in 0.18um CMOS technology. The measurement results show that, when the chip delivers 10Gb/s PRBS7 data over a 6.3 inches FR4 channel, the output peak-to-peak jitter is 34ps. This circuit also works as a driver and has a good impendence matching. The power consumption of the equalizer is 30.2mW for 1.8V supply.

Keywords

CMOS analogue integrated circuits; driver circuits; equalisers; impedance matching; transfer functions; CMOS integrated circuit; analog equalizer; bandwidth enhancement; bit rate 10 Gbit/s; circuit design; continuous time linear equalizer; design guidance; double series peaking network; driver circuit; impedance matching; power 30.2 mW; size 0.18 mum; transfer function; voltage 1.8 V; Bandwidth; CMOS integrated circuits; Capacitance; Equalizers; Equations; Jitter; Mathematical model;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC (ASICON), 2013 IEEE 10th International Conference on

Conference_Location

Shenzhen

ISSN

2162-7541

Print_ISBN

978-1-4673-6415-7

Type

conf

DOI

10.1109/ASICON.2013.6811888

Filename

6811888