DocumentCode
2065401
Title
A resource optimized SoC Kit for FPGAs
Author
Hempel, Gerald ; Hochberger, Christian
Author_Institution
Dresden Univ. of Technol., Dresden
fYear
2007
fDate
27-29 Aug. 2007
Firstpage
761
Lastpage
764
Abstract
Modern FPGAs have become so affordable that they can be used to substitute ASICs in mass produced devices. A key component of such configurable system on a chip (CSoC) is the processor core. Available and usable cores are either 32 or 8 bit wide. Thus, there is a gap between these two extremes, which we want to fill with our SoC kit. In this contribution we elaborate on our SoC kit and its components and compare it to other SoC design environments.
Keywords
field programmable gate arrays; logic design; system-on-chip; FPGA; SoC kit; field programmable gate array; processor core; system-on-chip design; Availability; Computer architecture; Costs; Embedded system; Field programmable gate arrays; Fitting; Manufacturing processes; Process design; Reduced instruction set computing; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Field Programmable Logic and Applications, 2007. FPL 2007. International Conference on
Conference_Location
Amsterdam
Print_ISBN
978-1-4244-1060-6
Electronic_ISBN
978-1-4244-1060-6
Type
conf
DOI
10.1109/FPL.2007.4380763
Filename
4380763
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