Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates

Gate leakage (direct tunneling current for sub-65 nm CMOS) can severely affect both the transient and steady state behaviors of CMOS circuits. In this paper we quantify the transient and steady-state gate leakage effects as capacitances and state independent (equiprobable) average values, respectively. These metrics are characterized for two universal logic gates, 2-input NAND and NOR, and their sensitivity to variations in process and design parameters is studied. The effective tunneling capacitance of a logic gate is defined as the maximum change in tunneling current with respect to the rate of change of input voltage. It is an unique and novel metric and to our knowledge proposed here for the first time with respect to a logic gate. This metric concisely encapsulates both qualitative as well as quantitative information about the swing in tunneling current during state transitions while simultaneously accounting for the transition rate and represents the capacitive load of the logic gate due to transience in tunneling.