A test pattern selection method for dynamic burn-in of logic circuits based on ATPG technique

Author

Xuan Yang ; Xiaole Cui ; Chao Wang ; Chung-Len Lee

Author_Institution

Shenzhen Grad. Sch., Key Lab. of Integrated Microsyst., Peking Univ., Shenzhen, China

fYear

2013

fDate

28-31 Oct. 2013

Firstpage

1

Lastpage

4

Abstract

State transition of nodes in the circuit generates heat which usually needs to be minimized for reliability consideration. In this work, instead, the heat generated is used to burn-in the CUT. A burn-in test pattern selection technique based on the ATPG approach for maximizing the dynamic power of the CUT is proposed. Experimental results show that the technique is effective in selecting the patterns which offer maximal power. It can be applied into the burn-in of logic circuits and SoCs in an energy saving manner.

Keywords

automatic test pattern generation; circuit reliability; logic circuits; logic testing; ATPG technique; CUT; SoCs; burn-in test pattern selection technique; dynamic burn-in of logic circuits; energy saving; maximal power; node state transition; Automatic test pattern generation; Circuit faults; Integrated circuit modeling; Logic gates; Power dissipation; Simulation; Vectors; ATPG; Burn-in; Dynamic Power;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC (ASICON), 2013 IEEE 10th International Conference on

Conference_Location

Shenzhen

ISSN

2162-7541

Print_ISBN

978-1-4673-6415-7

Type

conf

DOI

10.1109/ASICON.2013.6811958

Filename

6811958