EP1: Moore´s law challenges below 10nm: Technology, design and economic implications

Moore´s Law has governed advances of silicon technology for more than four decades, providing a tremendous reduction in cost per transistor. Device geometry, packing density, speed performance, and manufacturing cost of a single transistor have scaled together-according to Dennard scaling rule. Approaching the sub-10nm era and beyond, Moore´s Law faces serious challenges in the near future (5–6 years). Device geometry/density/performance/cost will not scale simultaneously anymore. What are the new scaling rules for logic and memory? Researchers are racing to address 3 scenarios: 1) extending silicon, 2) beyond silicon, and 3) beyond CMOS.