Enhanced error correction against multiple-bit-upset based on BCH code for SRAM

With scaling down of device and increasing memory density, reliability of SRAM faces severe challenge from soft errors, for radiation particles may upset multiple adjacent memory cells, and this limits the efficacy of conventionally used error correcting codes. This paper, based on the double error correcting (DEC) BCH codes, presents a solution to find codes which can correct, in addition to double random errors, a burst error of length up to three bits for 16, 32-bit memories or a burst error of length up to four for 16, 32 and 64-bit memories. The codes have been implemented in parallel architecture with a 90nm CMOS technology, and the result shows that they incurs almost the same latency and area overhead as compared to the conventional DEC BCH code which only correct double random errors.