• DocumentCode
    2068900
  • Title

    Transfer-printed microscale integrated circuits

  • Author

    Bower, C.A. ; Menard, E. ; Bonafede, S. ; Burroughs, S.

  • Author_Institution
    Semprius, Inc., Durham, NC
  • fYear
    2009
  • fDate
    26-29 May 2009
  • Firstpage
    618
  • Lastpage
    623
  • Abstract
    Transfer-printing is an emerging technology that enables massively parallel assembly of microscale semiconductor devices onto virtually any target substrate, including glass, plastics, metals or other semiconductors. Transfer-printing is accomplished using a microstructured elastomeric stamp to selectively pick-up devices from a source wafer and then print the devices onto a target substrate. The process is massively parallel as the stamps are designed to transfer hundreds to thousands of discrete devices in a single pick-up and print operation. Previous studies using bare silicon chips [1] demonstrated transfer-print yields in excess of 99% and chip placement accuracy better than plusmn 5 mum. For the first time, foundry-produced CMOS integrated circuits have been designed and transfer-printed. The ICs were designed and built using a commercially available silicon-on-oxide (SOI) CMOS process. The buried oxide (BOx) underneath the device layer is used as a sacrificial layer to ldquoreleaserdquo the ICs from the handle wafer. Microfabricated silicon bridges, or tethers, are used to fasten the ICs to the handle wafer following the sacrificial etch. A process was developed to remove the sacrificial BOx while protecting the interlayer dielectric (ILD) and Aluminum wiring levels present in the ICs. The microscale ICs have been transfer-printed with yields in excess of 99.5% and with placement accuracies better than plusmn 5 mum. Surface topography present on the ICs did not negatively impact the transfer-printing process. Initial studies show that transfer-printing has negligible impact on the I-V characteristics of transistors.
  • Keywords
    CMOS integrated circuits; aluminium; buried layers; silicon; silicon-on-insulator; surface topography; transistors; Al; I-V characteristics; Si; aluminum wiring levels; buried oxide; foundry-produced CMOS integrated circuits; interlayer dielectric; microfabricated silicon bridges; microscale semiconductor devices; microstructured elastomeric stamp; silicon-on-oxide CMOS process; surface topography; tethers; transfer-printed microscale integrated circuits; transistors; Assembly; CMOS integrated circuits; CMOS process; Glass; Integrated circuit technology; Integrated circuit yield; Plastics; Semiconductor devices; Silicon; Substrates;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference, 2009. ECTC 2009. 59th
  • Conference_Location
    San Diego, CA
  • ISSN
    0569-5503
  • Print_ISBN
    978-1-4244-4475-5
  • Electronic_ISBN
    0569-5503
  • Type

    conf

  • DOI
    10.1109/ECTC.2009.5074077
  • Filename
    5074077