Two new techniques to reduce gate leakage at 65 nm technology

Overall power consumption in nano-scaled device is reaching an alarming state due to the increasing trend of various leakage current. Along with dynamic power, leakage power has turned out to be a major contributor to the overall power in VLSI circuits. This problem is even more stringent in nano-scale devices according to the International Technology Roadmap for Semiconductors (ITRS). Technology advancement demands more function per device with a significant shrinking in device dimension. This turns out into degradation of device material viz, di-electric breakdown, altered component characteristics etc due to excessive heat. This demands additional cooling arrangements to keep heat to a minimal operational range. Due to increased power consumption, the battery power also gets drained at a rapid rate. This demands bulky power sources in miniature devices, which is a great hindrance in hand-held portable gadgets. Static power dissipation occurs in standby mode as well as in active mode of operation of the device. In this work we have proposed two run time leakage current reduction techniques for the CMOS logic circuit at 65 nm technology. As a basic reference, we have selected NAND (universal gate) as our point of focus. We have compared the leakage value of the proposed NAND gates with normal NAND. Maximum leakage saving has been obtained more than 45%. The technique is also well suited for the reduction of dynamic power. Simulation results show up to 21% in dynamic power saving with small area and delay overhead.