Characterization of a low leakage current and high-speed 7T SRAM circuit with wide voltage margins

A seven transistor (7T) static random-access memory (SRAM) cell with single-ended read and write operations is evaluated in this paper. The cell topology consists of a single bitline, a cross-coupled inverter pair with a transmission gate employed in the feedback path, and a bitline access transistor. Simulation results with 8 Kib SRAM arrays indicate up to 49.3% reduction in leakage currents, 42.7% shorter read delay, 36.9% lower write delay, and 75.4% wider voltage margin during write operations with the 7T SRAM cells while providing similar read static noise margin (RSNM) characteristics as compared to the conventional six transistor (6T) SRAM cells in TSMC 65nm standard CMOS technology. These performance benefits are achieved at the cost of 63.0% larger cell area, 70.6% higher read power consumption, and 57.9% higher write power consumption as compared to the conventional 6T SRAM cells.