DocumentCode
2071446
Title
Process-variability aware delay fault testing of ΔVT and weak-open defects
Author
Arumí-Delgado, Daniel ; Rodríguez-Montañés, Rosa ; De Gyvez, José Pineda ; Gronthoud, Guido
Author_Institution
Dept. of Electron. Eng., Polytech. Univ. of Catalunya, Barcelona, Spain
fYear
2003
fDate
25-28 May 2003
Firstpage
85
Lastpage
90
Abstract
Circuits are tested for both functionality and performance. As opposed to circuits with large delay faults, circuits with small delay faults are difficult to diagnose and as such are potential test escapes. This paper presents a strategy to diagnose these types of defective circuits. Our approach takes into account the effect of inter and intra die process variability in the detection method. Unlike conventional delay fault testing, our approach propagates a delay fault in such a way that the mean of the statistical delay distribution of the faulty circuit is further increased with respect to the mean of a fault-free circuit. This is a two-step strategy that is derived from a simple fault model. The paper further presents simulation results supporting the delay fault testing.
Keywords
circuit simulation; fault diagnosis; integrated circuit modelling; integrated circuit testing; statistical analysis; delay fault propagation; delay fault testing; fault diagnosis; fault model; functional testing; inter die process variability; intra die process variability; performance testing; potential test escapes; process-variability aware testing; statistical delay distribution; weak-open defects; CMOS technology; Circuit faults; Circuit simulation; Circuit testing; Electronic equipment testing; Fault detection; Integrated circuit testing; Laboratories; Propagation delay; Semiconductor device modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Workshop, 2003. Proceedings. The Eighth IEEE European
ISSN
1530-1877
Print_ISBN
0-7695-1908-3
Type
conf
DOI
10.1109/ETW.2003.1231673
Filename
1231673
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