Equivalent circuit model extraction for interconnects in 3D ICs

Parasitic RC behavior of VLSI interconnects has been the major bottleneck in terms of latency and power consumption of ICs. Recent 3D ICs promise to reduce the parasitic RC effect by making use of through silicon vias (TSVs). It is therefore essential to extract the RC model of TSVs to assess their promise. Unlike interconnects on metal layers, TSVs exhibit slow-wave and dielectric quasi-transverse-electromagnetic (TEM) modes due to the coupling to the semiconducting substrate. This TSV behavior can be simulated using analytical methods, 2D electrostatic simulators, or 3D full-wave electromagnetic simulators. In this paper, we describe a methodology to extract parasitic RC models from such simulation data for interconnects in a 3D IC.