DocumentCode
2073511
Title
Performance analysis of a BiNMOS device
Author
Kuo, B. ; Rosseel, G.P. ; Dutton, R.W.
Author_Institution
Nat. Taiwan Univ., Taipei, Taiwan
fYear
1989
fDate
25-28 Sep 1989
Lastpage
38078
Abstract
The BiNMOS device associated with 2-μm n-well BiCMOS technologies consumes substantial area for isolation. A merged BiNMOS device structure is introduced to reduce device size. The performance of the merged BiNMOS device has been analyzed by PISCES-2B. DC characteristics show that the merged BiNMOS device has a higher driving capability. Turn-on transient analysis shows substantial substrate currents during transient
Keywords
BIMOS integrated circuits; bipolar transistors; insulated gate field effect transistors; integrated circuit technology; semiconductor device models; transients; 2 micron; BiNMOS device; DC characteristics; PISCES-2B; area for isolation; device size reduction; driving capability; merged BiNMOS device structure; n-well BiCMOS technologies; performance; performance analysis; substrate currents during transient; turn on transient analysis; BiCMOS integrated circuits; Degradation; Doping; Electrodes; Inverters; Isolation technology; MOS devices; Performance analysis; Threshold voltage; Transient analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Seminar and Exhibit, 1989. Proceedings., Second Annual IEEE
Conference_Location
Rochester, NY
Type
conf
DOI
10.1109/ASIC.1989.123176
Filename
123176
Link To Document