FPGA performance versus cell granularity

An experimental approach was used to investigate the relationship between the performance of an FPGA (field-programmable gate array) and its basic cell granularity. Over a large set of design examples it was found that a four or five input cell achieves minimum average critical path delay for a wide range of programmable switch time constant, τ _s. As expected, the `optimal´ cell granularity was found to increase gradually as τ_s increases