Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs

Author

Shin-Shiun Chen ; Chun-Kai Hsu ; Hsiu-Chuan Shih ; Jen-Chieh Yeh ; Cheng-Wen Wu

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

2013

fDate

22-25 Jan. 2013

Firstpage

429

Lastpage

434

Abstract

With the rapid popularization of mobile devices, the low-power and energy-efficient became far more important than the system operating frequency. This work demonstrates a processor and DRAM integration scheme by TSV-based 3-D stacking and the performance and energy efficiency is evaluated by an ESL design methodology. The integration scheme comprising Sans-Cache DRAM (SCDRAM) architecture which is designed under the power and energy considerations is explored. Experiment results show the proposed architecture can greatly reduce 80% energy while having 23.5% of system performance improvement.

Keywords

DRAM chips; logic design; low-power electronics; microprocessor chips; three-dimensional integrated circuits; DRAM integration; ESL design methodology; SCDRAM architecture; Sans-Cache DRAM; TSV-based 3D stacking; mobile devices; power-aware SOC; processor integration; system operating frequency; system performance improvement; Computer architecture; Decoding; Random access memory; Stacking; System-on-chip; Through-silicon vias; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific

Conference_Location

Yokohama

ISSN

2153-6961

Print_ISBN

978-1-4673-3029-9

Type

conf

DOI

10.1109/ASPDAC.2013.6509634

Filename

6509634