Neural network development using VHDL

Author

Avery, James M.

Author_Institution

NCR Corp., Ft. Collins, CO, USA

fYear

1989

fDate

25-28 Sep 1989

Lastpage

38078

Abstract

A developmental approach for hardware implementations of neural networks is presented. Neural network architectural representations including both behavioral and structural influences are presented using the VHSIC High-Level Description Language (VHDL). VHDL design entities and configurations are applied to neural network algorithm development and simulation. Neural network design interchange formats are discussed

Keywords

VLSI; digital integrated circuits; neural nets; specification languages; VHDL; VHSIC High-Level Description Language; behavioral influences; hardware implementations of neural networks; neural network algorithm development; neural network development; structural influences; Algorithm design and analysis; Circuit simulation; Circuit synthesis; Computational modeling; Convergence; Mathematical model; Neural networks; Process design; Software algorithms; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Seminar and Exhibit, 1989. Proceedings., Second Annual IEEE

Conference_Location

Rochester, NY

Type

conf

DOI

10.1109/ASIC.1989.123181

Filename

123181

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2074887