Understanding and minimizing ground bounce during mode transition of power gating structures

Author

Kim, Suhwan ; Kosonocky, Stephen V. ; Knebel, D.R.

Author_Institution

IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2003

fDate

25-27 Aug. 2003

Firstpage

22

Lastpage

25

Abstract

We introduce and analyze the ground bounce due to power mode transition in power gating structures. To reduce the ground bounce, we propose novel power gating structures in which sleep transistors are turned on in a non-uniform stepwise manner. Our power gating structures reduce the magnitude of peak current and voltage glitches in the power distribution network as well as the minimum time required to stabilize power and ground. Experimental simulation results with PowerSpice fixtured in a package model demonstrate the effectiveness of the proposed power gate switching noise reduction techniques.

Keywords

SPICE; integrated circuit design; integrated circuit modelling; integrated circuit noise; interference suppression; leakage currents; low-power electronics; system-on-chip; PowerSpice simulation; ground bounce minimization; ground stabilization; nonuniform stepwise turn-on; peak current glitches; peak voltage glitches; power distribution network; power gate switching noise reduction techniques; power gating structure mode transition; power stabilization; sleep transistors; Circuit noise; Circuit simulation; Clocks; Integrated circuit noise; Permission; Power system reliability; Power systems; Switches; System-on-a-chip; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on

Print_ISBN

1-58113-682-X

Type

conf

DOI

10.1109/LPE.2003.1231828

Filename

1231828