Strained-Si devices and circuits for low-power applications

Author

Kim, Keunwoo ; Joshi, Rajiv V. ; Chuang, Ching-Te

Author_Institution

IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2003

fDate

25-27 Aug. 2003

Firstpage

180

Lastpage

183

Abstract

Static and dynamic power for strained-Si devices are analyzed and compared with conventional bulk-Si technology. Optimum device design points are suggested by controlling physical/structural device parameters. Strained-Si CMOS circuits are studied, showing substantially-reduced power consumption due to the unique advantageous features of strained-Si devices. The trade-off between power and performance in strained-Si devices/circuits is discussed. Further, analysis and low-power design points are applied and extended to strained Si on SOI substrate (SSOI) CMOS technology.

Keywords

CMOS integrated circuits; MOSFET; integrated circuit design; internal stresses; low-power electronics; silicon-on-insulator; Si; dynamic power; low-power applications; low-power design; optimum device design; physical device parameters; power consumption; power performance trade-off; static power; strained Si on SOI substrate CMOS technology; strained-Si CMOS circuits; strained-Si MOSFET; structural device parameters; CMOS technology; Capacitance; Energy consumption; Germanium silicon alloys; Integrated circuit technology; MOSFET circuits; Permission; Photonic band gap; Silicon germanium; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on

Print_ISBN

1-58113-682-X

Type

conf

DOI

10.1109/LPE.2003.1231858

Filename

1231858