Exploiting 0.8-micron ASIC libraries from different venders

An ASIC (application-specific integrated circuit) library development methodology has been developed which requires no rework to import a library element from a different vender using the same process technology. A 0.8-μm scalable, high-density standard cell library using this methodology is discussed. The discussion covers the methodology used to establish compatibility in the areas of process, mask layout, scalable design rules, physical data, standard cell design, logic/delay simulation, and megacell design