DocumentCode
2076618
Title
Enhanced dynamic threshold UTBB SOI at high temperature
Author
Sasaki, K.R.A. ; Martino, J.A. ; Aoulaiche, M. ; Simoen, E. ; Claeys, C.
Author_Institution
LSI/PSI, Univ. of Sao Paulo, Sao Paulo, Brazil
fYear
2015
fDate
26-28 Jan. 2015
Firstpage
261
Lastpage
264
Abstract
This work focuses on the high temperature analysis in extensionless ultra-thin body and buried oxide (UTBB) SOI MOSFETs in dynamic threshold (DT) mode, as well as in enhanced DT (eDT) mode operation for the first time. In spite of the higher transconductance temperature degradation factor (c), the DT and eDT operations resulted in a lower VT variation with temperature and a lower Zero-Temperature-Coefficient (ZTC) point with the same current level for all k-values. Concerning the analog parameters, the transistor efficiency (gm/ID), Early voltage (VEA) and intrinsic voltage gain (Av) were degraded at high temperature. However, the improvement thanks to DT and eDT modes compensates and further enhances these parameters.
Keywords
MOSFET; high-temperature electronics; silicon-on-insulator; DT mode operation; ZTC; analog parameters; current level; eDT mode operation; enhanced dynamic threshold UTBB SOI; high temperature analysis; intrinsic voltage gain; k-values; silicon-on-insulator; transconductance temperature degradation factor; transistor efficiency; ultrathin body and buried oxide SOI MOSFET; zero-temperature-coefficient; Degradation; Logic gates; MOSFET; Temperature; Temperature sensors; Threshold voltage; Transconductance; DTMOS; UTBB FDSOI; high temperature;
fLanguage
English
Publisher
ieee
Conference_Titel
Ultimate Integration on Silicon (EUROSOI-ULIS), 2015 Joint International EUROSOI Workshop and International Conference on
Conference_Location
Bologna
Type
conf
DOI
10.1109/ULIS.2015.7063823
Filename
7063823
Link To Document