DocumentCode
2078240
Title
A gate array designed with built in testability
Author
Dwyer, Robert A.
Author_Institution
OKI Semicond., Stoneham, MA, USA
fYear
1989
fDate
25-28 Sep 1989
Lastpage
38108
Abstract
An examination is made of the limitations of manual test generation and the need for thorough testing. A review is conducted of built-in testability and improved fault coverage and scan path implementations. Size and performance improvement is assessed, along with automatic test vector generation
Keywords
automatic testing; fault location; logic arrays; logic testing; automatic test vector generation; built in testability; fault coverage; gate array; performance improvement; scan path implementations; Application specific integrated circuits; Automatic testing; Circuit faults; Circuit testing; Costs; Design engineering; Manufacturing processes; Power system modeling; Production; Semiconductor device packaging;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Seminar and Exhibit, 1989. Proceedings., Second Annual IEEE
Conference_Location
Rochester, NY
Type
conf
DOI
10.1109/ASIC.1989.123194
Filename
123194
Link To Document