Framed complexity analysis in SystemC for multi-level design space exploration

To guarantee efficient system-on-a-chip (SoC) solutions, design space exploration at various abstraction levels is needed. In this paper, we describe a simulation framework, which is particularly suited for multi-level exploration. Identifying the capturing of design metrics and their incorporation into an exploration framework as the main tasks to be resolved, we will propose a flexible monitoring tool implemented in SystemC to tackle the first item. We present a unified approach to capture and record behavioral, storage and communication characteristics at several abstraction levels of a typical SoC design flow. Figures such as increase in simulation time are included to characterize the developed tool. To address the design decision-making criteria, relevant design metrics are defined for each abstraction level. We distinguish among four distinct levels modeling algorithm and architecture transitions. Finally, iteration control aspects of Turbo decoders used in wireless systems serve as a case study.