DocumentCode
2080221
Title
An efficient algorithm for isomorphism-aware custom instruction identification for extensible processors
Author
Ahn, Junwhan ; Choi, Kiyoung
Author_Institution
Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea
fYear
2011
fDate
9-14 Oct. 2011
Firstpage
345
Lastpage
353
Abstract
Extensible processors have been widely used to achieve the conflicting demands for performance improvement, low power consumption, and flexibility. As extensible processors have become more popular, several algorithms have been proposed for automatically identifying instruction-set extensions in order to reduce the effort of manual design and verification. However, most of them focus on finding large and complex instructions that are used only once, rather than repeatedly used ones. Moreover, some other approaches that consider recurrence are limited to finding small instructions. This paper proposes a novel algorithm that considers the instruction reusability as well as I/O serialization. In order to overcome high complexity of the problem, we develop a canonical form construction algorithm for fast isomorphism detection on directed acyclic graphs and an incremental template generation algorithm that identifies the best custom instruction with a user-defined fitness function. Moreover, our algorithm serializes I/O operations so that the numbers of inputs and outputs of custom instructions are not limited by the microarchitecture. Experimental results show that our algorithm achieves significant improvement over previous approaches in terms of algorithm runtime as well as performance gain obtained by the custom instructions.
Keywords
directed graphs; instruction sets; multiprocessing systems; power aware computing; I/O serialization; canonical form construction algorithm; directed acyclic graph; extensible processor; incremental template generation algorithm; instruction reusability; instruction-set extension; isomorphism detection; isomorphism-aware custom instruction identification; low power consumption; performance improvement; user-defined fitness function; Algorithm design and analysis; Clustering algorithms; Complexity theory; Microarchitecture; Partitioning algorithms; Program processors; Registers; ASIPs; I/O serialization; extensible processors; instruction-set extension; isomorphism detection;
fLanguage
English
Publisher
ieee
Conference_Titel
Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2011 Proceedings of the 9th International Conference on
Conference_Location
Taipei
Print_ISBN
978-1-4503-0715-4
Type
conf
Filename
6062307
Link To Document