DocumentCode
2081123
Title
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)
fYear
1998
fDate
15-19 June 1998
Keywords
circuit CAD; circuit layout CAD; formal verification; integrated logic circuits; logic CAD; optimisation; ATPG; BDD; Boolean methods; collaborative design; deep submicron digital designs; design optimisation; design reuse; embedded system design; formal verification; functional simulation; functional verification; high level synthesis; interconnect modelling; logic optimisation; logic testing; mixed-signal design; partitioning; performance modelling; placement; power optimization; processor design; programable logic; state space methods; timing analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1998. Proceedings
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-89791-964-5
Type
conf
Filename
724428
Link To Document