Robust tests for stuck-open faults and design for testability of reconvergent fan-out CMOS logic networks

This paper addresses the problem of generating robust tests (tests which are efficient even in the presence of arbitrary delays) for stuck-open faults, in CMOS logic networks. The authors´ approach consists of a topological analysis leading to the definition of a criterion which allows them to distinguish between robustly and non-robustly testable gates. They also present a new design for testability method, to be applied to non-robustly testable gates