A comparison of recursive and repetitive models of recursive hardware structures

This paper examines techniques for developing VHDL descriptions of recursive hardware structures, using recursive and repetitive component instantiations. A fat tree interconnection network is examined as an example of a recursive hardware structure. The recursive description is easier to develop, and more clearly express the structure, making it easier to understand. The main difficulty in developing repetitive structures lies in devising a way of interconnecting the basic components comprising the structure. It is shown that the difficulties result from fundamental language design decisions made in VHDL, and that it is not appropriate to modify the language to avoid the difficulties. Hence, in general, the recursive style is preferred over the repetitive style for describing recursive hardware structures