• DocumentCode
    2082741
  • Title

    Cell-shifting compaction of building-cell methodology for high-speed GaAs standard-cell LSIs

  • Author

    Sasaki, Tadahiro ; Kawakyu, Katsue ; Seshita, Toshiki ; Kameyama, Atsushi ; Terada, Toshiyuki ; Kitaura, Yoshiaki ; Ishida, Kenji ; Uchitomi, Naotaka

  • Author_Institution
    Toshiba Corp., Kawasaki, Japan
  • fYear
    1991
  • fDate
    12-15 May 1991
  • Abstract
    The authors propose a novel cell-shifting compaction concept for building-cell methodology to realize high-speed GaAs standard-cell LSIs. This compaction reduces the layout-area and stray capacitance and the inductance of routings, and leads to a large degree of freedom for cell placement. The cell-shifting compaction is also a valid approach for Si standard-cell LSIs
  • Keywords
    III-V semiconductors; application specific integrated circuits; cellular arrays; circuit layout CAD; gallium arsenide; large scale integration; GaAs; Si; building-cell methodology; cell placement; cell-shifting compaction concept; inductance; layout-area; standard-cell LSIs; stray capacitance; Capacitance; Compaction; Gallium arsenide; Inductance; Large scale integration; Optimization methods; Routing; Shape; Ultra large scale integration; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 1991., Proceedings of the IEEE 1991
  • Conference_Location
    San Diego, CA
  • Print_ISBN
    0-7803-0015-7
  • Type

    conf

  • DOI
    10.1109/CICC.1991.164082
  • Filename
    164082