High-speed parallel CRC circuits

In this paper, we develop a matrix-based formulation for the Cyclic Redundancy Check (CRC) computation that is derived from its polynomial-based definition. Then, using this formulation, we propose a parallel CRC computation structure with optimizations specific to the case when the degree of parallelism is greater than the degree of the generator polynomial. Afterward, through extensive simulations we obtain the optimum degrees of parallelism in terms of their critical path delays for some common generator polynomials. We also show that the time-area product follows the critical path delay plot.