A 0.18µm pipelined 8B10B encoder for a high-speed SerDes

This paper presented a pipelined 8B10B encoder for a high speed SerDes. To overcome the drawback of the speed limitation due to the conventional architecture, a pipelined encoding architecture is proposed. By splitting the longer path into two shorter paths with registers, the delay of the critical path is shortened greatly. Based on the pipelined architecture, a high-speed 8B10B encoder is implemented using 0.18 μm CMOS technology and standard cell library. Post-simulation results show that the encoder can work up to the rate of 7Gbps with a core are of 76.86 μm × 76.86 μm and the power consumption is 5.0317 mW under a 1.8V power supply voltage.