Storage mechanism for VHDL intermediate form

This paper describes the storage and access mechanisms used for structured data throughout the VHDL CAD system developed at the Swedish Institute of Microelectronics. The author presents the implementation rationale and the main design choices. He gives an overview of the general architecture of all parts and tools, with special emphasis on the most prominent features. He then details the main components of the system. He presents and comments on results, and indicates possible enhancements