DocumentCode
2090179
Title
Path Runner: an accurate and fast timing analyser
Author
Deschacht, D. ; Pinede, P. ; Robert, M. ; Auvergne, D.
Author_Institution
Univ. des Sci. et Tech. du Languedoc, Montpellier, France
fYear
1990
fDate
12-15 Mar 1990
Firstpage
529
Lastpage
533
Abstract
As a necessary aid to system integration, the authors present a pattern-dependent timing analysis tool, organized around an explicit formulation of elementary units and allowing accurate and fast evaluation of CMOS data paths. It can process large circuits accurately in reduced CPU time, thus allowing safe and fast temporal evaluation of CMOS VLSI circuits
Keywords
CMOS integrated circuits; VLSI; circuit analysis computing; CMOS VLSI circuits; Path Runner; fast timing analyser; pattern-dependent timing analysis tool; system integration; temporal evaluation; Algorithm design and analysis; Central Processing Unit; Circuits; Delay; Performance analysis; SPICE; Semiconductor device modeling; Switches; Timing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1990., EDAC. Proceedings of the European
Conference_Location
Glasgow
Print_ISBN
0-8186-2024-2
Type
conf
DOI
10.1109/EDAC.1990.136704
Filename
136704
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