Integration of ferroelectric capacitor technology with CMOS

Author

Moazzami, R. ; Maniar, P.D. ; Jones, R.E. ; Mogab, C.J.

Author_Institution

Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA

fYear

1994

fDate

7-9 June 1994

Firstpage

55

Lastpage

56

Abstract

Ferroelectric technology has several desirable features for low-power nonvolatile memories including low operating voltages (read and write as low as 1.5 V), high-speed write operation (intrinsic switching times <2 ns), long-term endurance (>10/sup 13/ read/write cycles), and small cell size (potentially near DRAM densities). Realization of practical memories employing ferroelectric technology requires successful integration with CMOS. However, very little has been reported on the process integration issues unique to ferroelectric technology. This paper is the first detailed report of these integration issues. The paper discusses the impact of CMOS backend processing on ferroelectric capacitors as well as the effect of capacitor fabrication on transistor characteristics.<>

Keywords

CMOS integrated circuits; cellular arrays; circuit reliability; ferroelectric storage; ferroelectric thin films; integrated circuit technology; integrated memory circuits; CMOS; backend processing; capacitor fabrication; cell size; ferroelectric capacitor technology; high-speed write operation; long-term endurance; low-power nonvolatile memories; operating voltages; process integration issues; Annealing; CMOS technology; Capacitors; Dielectrics; Electrodes; Etching; Ferroelectric films; Ferroelectric materials; Polarization; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1994. Digest of Technical Papers. 1994 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-1921-4

Type

conf

DOI

10.1109/VLSIT.1994.324380

Filename

324380