Developing a 3D layout for wafer fabrication plants

Author

Puzailov, Emanuel Paz ; Golany, Boaz ; Gurevich, Alexey

Author_Institution

INTEL Corp., Kiryat Gat

fYear

2005

fDate

13-15 Sept. 2005

Firstpage

281

Lastpage

284

Abstract

Wafer fabrication plants (FABs) are arranged in a two-dimension (2D) layout, usually in a single floor. These layouts imply various constraints on the work-in-process (WIP) and the material handling systems. In contrast, automated storage/retrieval systems (AS/RS) arranged in a three-dimension (3D) layout aisle, where each aisle is served by a robotic arm that moves back and forth between the aisle´s entrance point and its storage locations. This paper offers an AS/RS-based 3D layout for FABs. First, we formulate the general 3D layout design problem and develop a heuristic algorithm to solve it. Then, we evaluate the proposed layout comparative to its 2D counterpart. Finally, we test the proposed layout by simulating an actual data taken from the semiconductor industry and comparing the performance of 2D and 3D layouts, 30% throughput time reduction observed

Keywords

design; facilities layout; industrial manipulators; integrated circuit manufacture; materials handling; production facilities; storage automation; work in progress; aisle entrance point; automated retrieval systems; automated storage systems; heuristic algorithm; material handling systems; robotic arm; semiconductor industry; single floor layout; storage locations; three-dimension layout; two-dimension layout; wafer fabrication plants; work-in-process; Algorithm design and analysis; Engineering management; Fabrication; Floors; Heuristic algorithms; Industrial engineering; Materials handling; Production; Robotics and automation; Storage automation;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Manufacturing, 2005. ISSM 2005, IEEE International Symposium on

Conference_Location

San Jose, CA

Print_ISBN

0-7803-9143-8

Type

conf

DOI

10.1109/ISSM.2005.1513357

Filename

1513357