A Novel 1.8 V, 1066 Mbps, DDR2, DFI-Compatible, Memory Interface

An innovative design of a 533 MHz DDR2 SDRAM PHY based on a common standard bus interface (DFI) and implemented in 90 nm standard CMOS process, is presented in this paper. Off-chip driver with calibrated strength, slew rate control, and on-die termination mechanism are utilized to provide improved signal integrity. Furthermore a DDR3-like I/O architecture and an appropriate calibration mechanism has been employed in order to reduce input capacitance. A Register-Controlled Delay Locked Loop (RCDLL) is included that measures the period of the external DFI clock to generate two stable clock phases (0°, 90°) and aligns it with the internal PHY clock. A novel Dynamic Strobe Masking System (DSMS) has also been employed which, in contrast to traditional techniques, dynamically adjusts the length of the masking signal in real-time, based on the incoming strobe. Finally, the PHY provides the necessary hooks for data capture training by an external calibration engine. Post layout simulation results demonstrate its robustness over process, voltage, and temperature variations.