Optimal synthesis of high performance architectures

A formal integer programming (IP) model, which simultaneously schedules and allocates functional units, registers, and buses is presented for synthesizing cost-constrained globally optimal architectures. This research is important for industry by providing optimal schedules which minimize interconnect costs and interface to analog and asynchronous processes, since these are seen as key to synthesizing high-performance architectures. A partially structured tight IP formulation of the architectural synthesis problem provides globally optimal schedules for piecewise linear cost functions, using branch and bound, in execution times faster than previous research