• DocumentCode
    2091882
  • Title

    Advanced patterning solutions for self-aligned MOS structures in flash memory

  • Author

    Yeh, Edward K. ; Howard, Bradley J. ; McGarvey, Gordon ; Hill, Ervin ; Freidjung, Inbal ; Lane, Melissa

  • Author_Institution
    California Technol. & Manufacturing, Intel Corp., Santa Clara, CA, USA
  • fYear
    2005
  • fDate
    13-15 Sept. 2005
  • Firstpage
    442
  • Lastpage
    445
  • Abstract
    The self-aligned MOS (SMS) structure in flash memory is a complex stack that requires novel patterning solutions. For the 90-nm node, we were able to implement an industry-leading 193-nm lithography process. At the 65-nm node, technical constraints drove a significant process flow change which incorporates an enhanced hardmask (EHM) layer. The benefit realized from this change is a wider process window for both lithography and etch.
  • Keywords
    MOS integrated circuits; etching; flash memories; nanolithography; 193 nm; 65 nm; 90 nm; enhanced hardmask layer; flash memory; nanolithography process; process flow change; self-aligned MOS structures; Coatings; Dielectrics; Etching; Flash memory; Isolation technology; Lithography; Manufacturing industries; Resists; Silicon; Surfaces;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Semiconductor Manufacturing, 2005. ISSM 2005, IEEE International Symposium on
  • Print_ISBN
    0-7803-9143-8
  • Type

    conf

  • DOI
    10.1109/ISSM.2005.1513400
  • Filename
    1513400
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2091882