Macro-Model of Cell-Based Logic Block for Power Ground Network Analysis

This paper presents an efficient method to reduce the circuit scale of cell-based logic block for hierarchical transient analysis of VLSI power ground network. The method built logic block circuit model with considering inductance characteristics of power ground network in low metal layers and statistical distribution of active logic cells. It transformed circuit model into a simple one with only two nodes left by the method of circuit equivalent, and built the logic block macro-model, which could be processed in parallel for the independence relationship between different logic blocks. Substituting the macro-model for detailed circuits in the high level transient analysis, the computation complexity and runtime can be greatly reduced for nodes reduction and parallelism. Experimental results show that the runtime of PNHTA with macro-modeling technique is 2.47 and 118.08 times faster in serial and parallel respectively than PNFTA, and the maximum error is 0.57% compared with HSPICE. On the other hand, cell model with time varying current source is more practical than constant current source with less 62.25% voltage drop.