Memory card address bus design

The interaction of signal line impedance, crosstalk, chip capacitive loading and driver circuit output impedance on the operation of a memory address bus is demonstrated. The ASTAP circuit simulation program is used for detailed studies. The results of three parallel address lines connected to memory chips for unterminated far ends are discussed. Signal-line impedance decreases when adjacent lines are introduced. Choosing the correct driver circuit output impedance and terminating resistance affects the signal-line voltage and switching. The memory chips add capacitive loading to the line, which also reduces the impedance and affects the delay of the line. Simultaneous switching of the address lines adds delay to the system as well. Some design parameters based upon these interactions are discussed