Modeling and characterization of copper interconnects for SoC design

Interconnect (wiring) is central to nanometer system-on-a-chip (SoC) design. As such, accurate interconnect modeling and characterization are key to the design and verification of SoCs. Today copper (Cu) has become a mainstream material for on-chip interconnections. Unlike aluminum (Al) interconnects, Cu wire line width and thickness is a function of wire width and spacing, wire-pattern density, and topography. These new effects must be modeled accurately for designs to achieve first-time silicon success. In this paper, we discusses the Cu process and its impact on modeling the interconnect parasitic elements - resistance (R), capacitance (C), and inductance (L). For a given process node, the use of Cu reduces interconnect delay and power, but from a design prospective, the same effect is achieved by reducing wire length. The impact of the X-architecture, which makes pervasive use of diagonal lines and has the promise of reducing wire length by an average of 20%, is also discussed. Finally, silicon validation of the interconnect R, C, and L model, using a test-chip approach, is covered.