Computer aided design of sub-100 nm strained-Si/Si/sub 1-x/Ge/sub x/ NMOSFET through integrated process and device simulations

Integrated process and device simulations were performed to design sub-100 nm strained-Si/Si/sub 75/Ge/sub 25/ devices. The process and device models were carefully calibrated according to various physical and electrical device characterizations. It is observed that the dopant behavior is highly sensitive to the presence of the SSi/SiGe heterointerface, especially when the SSi thickness is reduced below 10 nm. This points to SSi thickness as a new source of process variation and careful control of the SSi layer is important to maintain consistent device performance. In addition, the Type-II energy-band alignment at the heterointerface also contributes strongly to the short-channel device behavior. This work illustrates the need for accurate heterostructure-based process and device models in order to simulate and design aggressively-scaled strained-Si devices.