FPGA implementation of Space Vector PWM algorithm for multilevel inverters using non-orthogonal moving reference frame

This paper presents the implementation of Space Vector PWM algorithm using non-orthogonal moving reference frame for diode-clamped multilevel inverter in Field Programmable Gate Array (FPGA). In this algorithm, the non-orthogonal reference voltage is obtained according to the sector where the reference voltage (V*) lies. From the triangle identification inside the hexagon, the Nearest Three Vectors are determined using the information of the sector and triangle where V* is located. The duty cycles are calculated by a set of simple equations. The softwares Quartus IIreg, ModelSimreg and MatLabreg were used to develop the algorithm. Fixed-point 16-bit signed patterns were used for calculus. A 10 MHz clock was used to obtain the switching time, whereas the PWM worked with a 50 MHz clock, in order to improve the PWM generation accuracy. The synchronism between switching time calculation and the PWM signal generation was carried out by a state machine. Alterareg Cyclonereg II with EP2C20F484C7N FPGA was used to generate the V* and develop the proposed algorithm. The results obtained with the DCI three-level inverter were satisfactory, validating the FPGA algorithm implementation. This algorithm can be extended to topologies of generic-ordered DCI multilevel inverters, very slightly altering its computational efforts.