• DocumentCode
    2098822
  • Title

    PCI express interface design and verification based on Spartan-6 FPGA

  • Author

    Jun, Li ; Wei, Wang

  • Author_Institution
    Sch. of Inf. & Commun. Eng., Tianjin Polytech. Univ., Tianjin, China
  • fYear
    2010
  • fDate
    11-14 Nov. 2010
  • Firstpage
    305
  • Lastpage
    307
  • Abstract
    A design and verification of PCI Express(PCIe) interface based on Xilinx Spartan-6 FPGA is presented. Sparant-6 FPGA contains integrated Endpoint Block for PCI Express and related IP-core, so a PCIe×1 data channel connector can be constructed in the add-in card without any other external chips. The PCItree debugging tool is used to verify the validity of the design.
  • Keywords
    field programmable gate arrays; industrial property; peripheral interfaces; IP-core; PCI express interface design; PCItree debugging tool; Spartan-6 FPGA; add-in card; integrated endpoint block; Benchmark testing; Data envelopment analysis; Economic indicators; Europe; Indexes; Industries; Resource management;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Communication Technology (ICCT), 2010 12th IEEE International Conference on
  • Conference_Location
    Nanjing
  • Print_ISBN
    978-1-4244-6868-3
  • Type

    conf

  • DOI
    10.1109/ICCT.2010.5689231
  • Filename
    5689231
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2098822