TETA: transistor-level engine for timing analysis

TETA is an interconnect-centric waveform calculator that was optimized to achieve the utmost efficiency for analyzing logic stages comprised of transistors and large coupled RC(L) interconnect models. TETA applies a novel compaction for the transistor clusters and employs successive chord iterations to solve the resulting nonlinear equations. These algorithms permit the use of simple SIMO (single input multi-output) N-port interconnect models since macromodel passivity is not required. The successive chord analysis also enables TETA to avoid the N-port matrix factorization during nonlinear iterations and allows the use of simple table look-up models for MOS devices. Complex gates and nonlinear capacitors can be handled without loss of generality.