Equalization and clock recovery for a 2.5-10Gb/s 2-PAM/4-PAM backplane transceiver cell

Author

Zerbe, J. ; Werner, C. ; Stojanovic, V. ; Chen, F. ; Wei, J. ; Tsang, G. ; Kim, D. ; Stonecypher, W. ; Ho, A. ; Thrush, T. ; Kollipara, R. ; Yeh, G.-J. ; Horowitz, M. ; Donnelly, K.

Author_Institution

Rambus, Los Altos, CA, USA

fYear

2003

fDate

13-13 Feb. 2003

Firstpage

80

Abstract

A backplane transceiver uses a folded 5-tap TX equalizer and 5-tap RX equalizer to counteract losses and reflections. A flexible 2-PAM/4-PAM CDR uses select transitions for receive clock recovery. BER better than 10/sup -15/ at 10 Gb/s and power <60 mW/Gb are measured values for a 16" backplane with two high speed connectors.

Keywords

FIR filters; decision feedback equalisers; digital-analogue conversion; pulse amplitude modulation; synchronisation; transceivers; 16 in; 2-PAM/4-PAM backplane transceiver cell; 2.5 to 10 Gbit/s; 5-tap RX equalizer; BER; clock recovery; decision feedback-based receive equalization; equalization; folded 5-tap TX equalizer; high speed connectors; select transitions; Backplanes; Clocks; Decision feedback equalizers; Delay; Digital filters; Dispersion; Eyes; Reflection; Transceivers; Transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-7707-9

Type

conf

DOI

10.1109/ISSCC.2003.1234216

Filename

1234216