DocumentCode
2104814
Title
Dynamic-sleep transistor and body bias for active leakage power control of microprocessors
Author
Tschanz, J. ; Narendra, S. ; Yibin Ye ; Bloechel, B. ; Borkar, S. ; De, V.
Author_Institution
Intel Corp., Hillsboro, OR, USA
fYear
2003
fDate
13-13 Feb. 2003
Firstpage
102
Abstract
Sleep transistors and body bias are used to control active leakage for a 32b integer execution core implemented in a 100nm dual V, CMOS technology. A PMOS sleep transistor degrades performance by 4% but offers 20/spl times/ leakage reduction which is further improved with body bias. Time constants for leakage convergence range from 30ns to 300ns allowing 9-44% power savings for idle periods greater than 100 clock cycles.
Keywords
CMOS digital integrated circuits; leakage currents; microprocessor chips; 100 nm; 30 to 300 ns; 32 bit; CMOS technology; active leakage power control; body bias; clock cycles; dynamic-sleep transistor; idle periods; integer execution core; leakage convergence; microprocessors; CMOS technology; Clocks; Frequency; MOS devices; Microprocessors; Power control; Power grids; Power measurement; Sleep; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-7707-9
Type
conf
DOI
10.1109/ISSCC.2003.1234225
Filename
1234225
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